This invention relates to integrated circuits and fabrication methods therefor, and more particularly to contact structures for integrated circuits and fabrication methods therefor.
Metal silicide contacts are widely used in integrated circuits for low resistivity contacts. Moreover, self-aligned silicide or salicide technology is widely used to form low resistance source, drain and gate contacts for integrated circuit field effect transistors. In a salicide process, metal is deposited over an integrated circuit field effect transistor and reacted with the exposed silicon areas of the source and drain as well as the exposed polysilicon gate electrode, to form a silicide. Metal silicide and salicide technology are described in Chapter 11 of the textbook entitled Silicon Processing for the VLSI Era, Volume I: Process Technology by Wolfe and Tauber, 1986, pages 384-406, the disclosure of which is hereby incorporated herein by reference.
When used in highly integrated field effect transistors, the silicide structure can produce low contact resistance with the source and drain regions and low sheet resistance in the bulk source/drain regions. These low resistances can reduce parasitic series resistance, shorten delay times and improve operational speed.
Integrated circuit fabrication has emphasized titanium silicide (TiSi2) and cobalt silicide (CoSi2) for silicide structures. In particular, titanium silicide exhibits low resistivity, strong tolerance to hot carrier degradation and stable silicidation. Unfortunately, shorts between the gate and source/drain electrodes can occur due to reaction between titanium (Ti) and the gate oxide sidewall spacer during silicide formation. Moreover, the contact resistance between titanium silicide and platinum may increase at temperatures over 800xc2x0 C. Titanium is therefore preferably annealed to form silicide in an oxygen-free ambient to reduce oxidation thereof. Titanium also may be susceptible to electromigration, and defects can occur in edge portions of titanium disilicide due to stress. Finally, if more than 700 xc3x85 of titanium silicide is formed on shallow source/drain junctions of less 0.21 xcexcm, the silicon substrate can be overconsumed thereby increasing leakage current and contact resistance.
On the other hand, cobalt silicide has a low resistivity of between about 16 and 18 xcexcxcexa9-cm and is stable at high temperatures. Moreover, cobalt (Co) can reduce short circuits between the gate and the source/drain electrodes. Cobalt silicide can form a relatively smooth contact with silicon compared to titanium silicide, without unduly disturbing the source/drain regions. See the publication entitled Degradation of Doped Si Regions Contacted with Transition-Metal Silicides Due to Metal-Dopant Compound Formation to Maex et al., Journal of Applied Physics, Vol. 66, No. 11, pages 5327-5334, 1989. Cobalt silicide may be less sensitive to plasma etching compared to titanium silicide and may exhibit less stress. Finally, competitive reactions other than silicide reactions may not occur in cobalt sicilide, unlike titanium sicilide which can form titanium nitride as a byproduct of the silicide forming reaction.
Unfortunately, cobalt silicide may have its own problems. First, it may be difficult to form a silicide layer having the proper thickness on the gate and on the source/drain regions in one step. This is because the gate may use a thick silicide layer to reduce wiring resistance and the source and drain regions may use a thin silicide layer so as to prevent overconsumption of the silicon wafer. To solve this problem, a method is proposed in a publication entitled Activation Energy for the C49-to-C54 Phase Transition of Polycrystalline TiSi2 Films with Under 30 nm Thickness to Matsubara et al., Materials Research Society Symposium Proceedings, Vol. 311, pages 263-268, 1993. Disclosed is a two-step process that forms a thick silicide layer on the gate and a thin silicide layer on the source/drain.
Moreover, silicidation may not occur uniformly because the cobalt silicide may not remove the native oxide on the silicon wafer. A rough interface may thereby be formed which can increase the thermal resistance, the contact resistance and the leakage current. In order to remove the native oxide layer the silicon substrate may be dipped in diluted hydrofluoric acid or sputter etched before forming the silicide.
Finally, at temperatures above 400xc2x0 C. the cobalt silicide may react with an aluminum conductive line so that diffusion barriers may need to be formed between the cobalt silicide and the aluminum to allow high temperature annealing. See the publication entitled Application of Self-Aligned CoSi2 Interconnection in Sub-Micron CMOS Transistors by Broadbent et al., Proceedings of the IEEE V-MIC Conference, Pages 175-182, 1988.
Methods have been developed which use cobalt/refractory metal double-metal layers. The use of a cobalt/refractory metal double-metal layer can provide a smooth interface with the silicon substrate and can reduce overconsumption of the silicon by controlling the silicidation reaction. Moreover, a diffusion barrier layer can be formed on the silicide layer by controlling the annealing ambient. As is well known to those having skill in the art, the refractory metals include titanium (Ti), zirconium (Zr), vanadium (V), hafnium (Hf), niobium (Nb) and tantalum (Ta).
Methods of forming cobalt/refractory metal double-metal layers will now be described. First, a thin refractory metal layer is formed on a silicon substrate. Then, a thin cobalt layer is formed thereon thereby forming a cobalt/refractory double-metal layer. A rapid thermal anneal is conducted on the double-metal layer in a nitrogen ambient. The silicidation temperature of the cobalt/refractory double-metal layer is higher than that of the cobalt layer so that cobalt is the main diffusion source during cobalt silicide formation. The diffusion coefficient of the cobalt is also greater than that of the refractory metal and silicon. Therefore the position of the refractory metal and the cobalt become reversed to produce a xe2x80x9clayer inversionxe2x80x9d phenomenon. Stated differently, the cobalt diffuses downward and the refractory metal diffuses upward.
Moreover, because the refractory metal exhibits a high oxidation ratio compared with the silicon, the refractory metal also removes the native oxide layer, thereby cleaning the silicon wafer. Then, the cobalt diffuses through the refractory metal layer and reacts with the silicon wafer to thereby form cobalt silicide. The refractory layer limits diffusion of the cobalt, thereby reducing breakdown of the shallow junction. Also, a nitride layer is formed on the cobalt silicide during annealing. The nitride layer can serve as a diffusion barrier layer and can prevent agglomeration of the silicide layer.
In order to form the cobalt/refractory metal double-metal layer, the silicidation is preferably performed by thermally annealing. Thus, the refractory metal should have a high oxidation rate compared with the silicon wafer. The silicidation temperature of the refractory metal should also be high compared with cobalt, thereby causing the layer inversion phenomenon. Also, the main diffusion source should be the silicon and not the refractory metal, so as to prevent reverse diffusion of the refractory metal into the silicon wafer during the annealing. Finally, the diffusion coefficient of the cobalt in the refractory metal should be large to thereby allow layer inversion to take place.
Of the refractory metals, titanium, zirconium, vanadium, hafnium, niobium and tantalum may possess the above characteristics. Titanium is generally used as the refractory metal in the cobalt/refractory metal double-metal layer process. Titanium can be easily oxidized so that the native oxide layer can be removed to thereby form an epitaxial silicide layer. The titanium also reacts readily with the cobalt, to thereby allow a complete layer inversion. Accordingly, sheet resistance can be low and the titanium nitride layer is formed on the cobalt silicide layer.
Unfortunately, when using titanium as a refractory metal, an undesirable reaction that consumes the silicon wafer can occur. This wafer consumption can degrade the shallow source and drain regions thereby increasing leakage current.
FIGS. 1A-1E graphically illustrate X-Ray Diffraction (XRD) spectra for a conventional cobalt/titanium double-metal layer process. A 120 xc3x85 thick titanium layer and 250 xc3x85 thick cobalt layer are used. Annealing is performed for 30 seconds at temperatures of 900xc2x0 C., 800xc2x0 C., 700xc2x0 C., 600xc2x0 C. and no rapid thermal annealing in FIGS. 1A-1E, respectively.
As shown in FIGS. 1A-1E, the XRD spectra show stable phase cobalt silicide at each annealing temperature. However, especially in FIG. 1D, a cobalt-titanium-silicon peak is detected. This indicates that additional undesirable reaction is taking place that consumes the silicon wafer during the annealing process. As a result, the silicon wafer may be overconsumed thereby degrading the device characteristics. Moreover, if the thickness of the cobalt/titanium double-metal structure is increased, some titanium may remain on the silicon wafer as xcex2-titanium. This may undesirably form titanium silicide or cobalt-titanium-silicide alloy on the silicide layer.
Accordingly, there continues to be a need for improved double-metal layer silicide and salicide processes and structures.
It is therefore an object of the present invention to provide methods of forming silicide layers for integrated circuits and salicide methods for forming source, drain and gate contacts for integrated circuit field effect transistors.
It is another object of the invention to provide improved metal silicide integrated circuit contact structures including field effect transistor source, drain and gate contact structures.
It is still another object of the present invention to provide double-metal silicide structures and double-metal salicide processes that can reduce consumption of the silicon wafer compared to conventional cobalt/titanium double-metal silicide structures and salicide processes.
These and other objects are provided according to the present invention by forming a first layer comprising niobium (Nb) on a silicon substrate and forming a second layer comprising a near noble metal on the first layer, opposite the silicon substrate. The near noble metal, also referred to as a Group VIII metal, is preferably cobalt (Co). The near noble metal has higher diffusion coefficient than the niobium and the silicon substrate. Annealing is then performed to diffuse at least some of the near noble metal through the first layer and react the diffused near noble metal with the silicon substrate to form a third layer comprising a near noble metal silicide, and to form a fourth layer comprising niobium-near noble metal alloy on the third layer. It has been found that the use of niobium can reduce substrate consumption compared to conventional cobalt titanium double-metal silicide fabrication processes.
The annealing step is preferably performed in a nitrogen containing ambient to also form a fifth layer comprising niobium nitride on the fourth layer, opposite the third layer. Moreover, when a native oxide layer is included on the silicon substrate, the annealing step can react the niobium with the native oxide and thereby remove the native oxide layer.
The above described methods can be used to form source, drain and gate contacts for integrated circuit field effect transistors including spaced apart source and drain regions in a silicon semiconductor substrate and an insulated polysilicon gate electrode on the silicon semiconductor substrate, between the spaced apart source and drain regions. A first layer comprising niobium is formed on the source and drain regions and on the polysilicon gate electrode. A second layer comprising a near noble metal is formed on the first layer, opposite the silicon substrate. The near noble metal has higher diffusion coefficient than niobium and the silicon substrate.
Annealing is performed to diffuse at least some of the near noble metal through the first layer and react the diffused near noble metal with the silicon and polysilicon to form a third layer comprising a near noble metal silicide on the source and drain regions and on the polysilicon gate electrode, and to form a fourth layer comprising niobium-near metal alloy on the third layer. The annealing may take place in nitrogen to also form a fifth layer comprising niobium nitride on the fourth layer, opposite the third layer. The annealing can also react the niobium with the native oxide to thereby remove the native oxide layer.
Integrated circuit contact structures according to the invention include a first layer comprising a near noble metal silicide on a silicon substrate and a second layer comprising niobium-near noble metal alloy on the first layer opposite the silicon substrate. A third layer comprising niobium nitride may also be provided on the second layer, opposite the first layer. The near noble metal is preferably cobalt and the structure is preferably free of the native oxide layer between the silicon substrate and the first layer. This contact structure may also be provided on the source and drain regions and on the polysilicon gate electrode of an integrated circuited field effect transistor. Improved silicides and salicide processes and structures may thereby be provided.